Japanese Patent Application No. 2001-393928, filed on Dec. 26, 2001, is herein incorporated by reference in its entirety.
The present invention relates to a ferroelectric memory device using ferroelectric capacitors in memory cells. More particularly, the present invention relates to a ferroelectric memory device capable of storing three or more values of data in one memory cell, and a method of driving the ferroelectric memory device.
In recent years, research and development of ferroelectric films such as PZT and SBT, ferroelectric capacitors using the ferroelectric films, and ferroelectric memory devices have been conducted extensively.
As a memory capable of storing multi-valued data, Japanese Patent Applications Laid-open No. 7-122661 and 8-180673 disclose memories in which a plurality of ferroelectric capacitors, for which the voltages required for polarization inversion differ, is connected in parallel and makes up one memory cell.
However, these technologies have the following problems. In the memory cells in which a plurality of ferroelectric capacitors for which the voltages required for polarization inversion differ is connected in parallel, the fabrication process is complicated when forming the ferroelectric capacitors for which the voltages required for polarization inversion differ, or the area occupied by a plurality of ferroelectric capacitors connected in parallel is increased, thereby increasing the cost of the ferroelectric memory device.
The present invention may provide a ferroelectric memory device capable of storing multi-valued data consisting of three of more values per memory cell and a method of driving the same without causing the fabrication process to be complicated nor increasing an area occupied by ferroelectric capacitors.
The present invention provides a ferroelectric memory device having a memory cell array in which a plurality of memory cells each of which has at least one ferroelectric capacitor are arranged,
wherein three or more values of data are selectively stored in the ferroelectric capacitor by applying voltages having three or more different values for setting three or more polarization states in the ferroelectric capacitor.
According to the present invention, three or more values of data can be stored by applying voltages having three or more different values for setting three or more polarization states in the ferroelectric capacitor, and by reading each of the polarization states as data. Each of the polarization states is set so that a sufficient margin which enables the data to be distinguished from each other at the time of reading is secured.
According to the present invention, since three or more values of data can be stored in the single ferroelectric capacitor, a higher degree of integration can be achieved without increasing the area occupied by the ferroelectric capacitors in comparison with a case of forming one memory cell by combining a plurality of ferroelectric capacitors.
Among the three or more polarization states, two polarization states may be saturation polarization states, and at least one polarization state may be a partial polarization state.
The present invention can be applied to the following ferroelectric memory devices, for example.
(A) Two-transistor, Two-capacitor (2T2C) Ferroelectric Memory Device
In this ferroelectric memory device, each of the memory cells may include one word line, two bit lines, one plate line, two transistors and two ferroelectric capacitors;
a gate of a first transistor may be connected to the word line, source/drains of the first transistor may be respectively connected to a first bit line and a first electrode of a first ferroelectric capacitor, and a second electrode of the first ferroelectric capacitor may be connected to the plate line; and
a gate of a second transistor may be connected to the word line, source/drains of the second transistor may be respectively connected to a second bit line and a first electrode of a second ferroelectric capacitor, and a second electrode of the second ferroelectric capacitor may be connected to the plate line.
(B) One-transistor, One-capacitor (1T1C) Ferroelectric Memory Device
In this ferroelectric memory device, each of the memory cells may include one word line, one bit line, one plate line, one transistor and one ferroelectric capacitor; and
a gate of the transistor may be connected to the word line, source/drains of the transistor may be respectively connected to the bit line and a first electrode of the ferroelectric capacitor, and a second electrode of the ferroelectric capacitor may be connected to the plate line.
(C) Simple Matrix Type Ferroelectric Memory Device
In this ferroelectric memory device, each of the memory cells may include one word line, one bit line, and one ferroelectric capacitor; and
the word line and the bit line may be respectively connected to a first electrode and a second electrode of the ferroelectric capacitor.
According to the present invention, there is provided a first method of driving a ferroelectric memory device having a memory cell array in which a plurality of memory cells each of which has at least one ferroelectric capacitor are arranged, the method comprising:
a first step of applying a predetermined voltage to the ferroelectric capacitor in a memory cell selected from the plurality of memory cells to put the ferroelectric capacitor in a polarization state;
a second step of selectively writing three or more values of data in the ferroelectric capacitor of the selected memory cell by applying voltages having three or more different values for setting three or more polarization states in the ferroelectric capacitor; and
a third step of applying a predetermined voltage to the ferroelectric capacitor in the selected memory cell to read out data based on variations in a polarization state of the ferroelectric capacitor.
The first method can be applied to the above-described ferroelectric memory devices in (B) and (C), for example.
According to the present invention, there is also provided a second method of driving the ferroelectric memory device described in (A), comprising:
a first step of applying a predetermined voltage to the first ferroelectric capacitor in a memory cell selected from the plurality of memory cells to put the first ferroelectric capacitor in a polarization state;
a second step of selectively writing three or more values of data in the first ferroelectric capacitor of the selected memory cell by applying voltages having three or more different values for setting three or more polarization states in the first ferroelectric capacitor, and also applying a predetermined voltage to the second ferroelectric capacitor to put the second ferroelectric capacitor in a polarization state; and
a third step of applying a predetermined voltage to the first and second ferroelectric capacitors in the selected memory cell to read out data based on variations in a polarization state of the first and second ferroelectric capacitors.
In the first and second methods, the third step may serve as the first step for a following writing process, and a writing process which is the same as the writing process of the second step may be performed after the third step. In this case, the voltage applied to the ferroelectric capacitor in the third step may be the same as the voltage applied to the ferroelectric capacitor in the first step.